Many semiconductor arrangements comprise numerous sequential cells, such flip flops, that are connected to circuitry, such as logic structures, by data paths. A full scan scheme is used to test a semiconductor arrangement for design defects and processing defects. In a full scan scheme, scan paths are connected to the sequential cells so that a test scan pattern can be directly provided to the sequential cells, as opposed to being provided through data paths that otherwise increase computational overhead because the effect of circuitry on the test scan pattern is taken into account. The full scan scheme provides relatively high test coverage because the test scan pattern is directly input into sequential cells. However, connecting additional scan paths to sequential cells for the full scan increases power consumption, decreases performance, and increases area overhead.